The present invention concerns electro-optic devices, having particular advantages in large-area display devices which are formed as an array of tiled display devices.
There is an unmet need for large-area flat displays. No clear solution is apparent in the market place. This unmet need is becoming increasingly critical since the advancement of information results in increasing amounts of data to be displayed. A solution for large-area displays is needed to serve as the human interface for conveying information from sensors, computers, databases, cameras, etc. in this information dominated age. Many critical applications demand large-area displays:
Home theater applications
Applications that require multiple viewers
Applications in which the user needs to move about in an area
Applications where simulation of the real world is needed for training.
The requirements for each application differ in size, shape, total number of picture elements (pixels), and brightness. Requirements that are common to most applications include, a relatively large number of pixels, color, ruggedness, portability (minimum thickness and weight), reliability, low power, and affordable cost. A good display solution does not exist for these needs using present technology.
There are fundamental technical issues that impose scaling-laws and limit the size of displays that can be manufactured. These fundamental limitations are one reason why a technical solution that meets the need for large-area displays has not been achieved.
One measure of the complexity of a display device is its total number of pixels. The evolution of display technology has made newer and more complex pixel formats possible—such as VGA, SVGA, XGA, and SXGA. Increased complexity typically is accompanied by added costs. The underlying cause of this empirical complexity law is yield losses caused by random material or particle defects. These defects cause manufacturing yields to diminish as the number of pixels in the display increases.
One measure of the size of a display is its area. Costs increase exponentially with size. Each technology, LCD, PDP, EL, etc., has its own limit on maximum size. The underlying technical cause of this empirical relationship is tolerance. It is desirable to hold tight tolerances in manufacturing displays because, as the size increases, the effects of thermal expansion, humidity, residual stresses, and physical sag become more important.
Building a large-area display out of smaller tiles has been recognized as a desirable solution. Tiling is an approach that provides great flexibility for size and shape. Tiling is not subject to many of the problems that limit the size of monolithic display technologies. The complexity law does not apply because, depending on the size of the tile, the basic unit of manufacture in tiled displays is less complex than a large, monolithic multi-pixel display. The size law is not a limiting factor because the basic unit of manufacture is relatively small. Tiled displays obey a scaling-law which is not exponential but linear with display area. This fundamentally different scaling behavior is one advantage of tile technology. It reduces manufacturing costs.
What has been missing in tiled displays is a fabrication technology that allows a display to be constructed so that pixels can be brought up to the very edge (actually, with in ½ pixel spacing period of the edge), while at the same time allowing for electronics to address each tile, even those tiles completely surrounded by other tiles. Two barriers to implementing the tiled approach have been: 1) eliminating the visibility of the seams between tiles, and 2) providing electrical access to the pixels.
One type of tiled display is disclosed in U.S. Pat. No. 5,644,327 entitled TESSELLATED ELECTROLUMINESCENT DISPLAY HAVING A MULTILAYER CERAMIC SUBSTRATE to Onyskevych et al., which is incorporated herein by reference for its teaching on tiled displays. This patent describes an electroluminescent display and a combination field emissive and electroluminescent display which are formed as tiles that may be joined together to provide a large-area display device. The exemplary tiles are formed using low-temperature co-fired ceramic and metal structures consisting of multiple layers of ceramic circuit-board material laminated to a metal core.
Driving circuitry for the displays is mounted on the back of the structures and vias are passed through the structure from the back to the front in order to make connection with the pixel electrodes on the front of the display device. The vias that make these connections pass between pixel positions on the display. In addition, connections are made on a pixel-by-pixel basis or for a small group of pixels. Thus, a display device according to the referenced patent may need a relatively large number of vias. The described tiles include connectors at their edges through which multiple tiles may be interconnected.